MMP2 Interrupt Controller forcing IRQ

[Andrei E. Warkentin]

2011/9/26 Andrei E. Warkentin <andrey.warkentin at gmail.com>:
> 2011/9/26 Mitch Bradley <wmb at firmworks.com>:
>>
>> If you write 0x400 to APB_VIRT_BASE + 0x1d008, it will assert interrupt 56 .
>>
>> You can then clear it by writing 0x400 to APB_VIRT_BASE + 0x1d40c.
>>
>> This uses an inter-processor communication unit.  Presumably the FIG handler
>> would assert the interrupt and the IRQ 56 handler would clear it.
>>
>
> Awesome! Thanks a lot!!!
>
>

Hmm. I was hoping that this was really GIC SGI functionality
(http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048a/index.html),
but I guess PJ4 has something completely different. Is there an easy
formula for the values written into those two regs and the IRQ value?
Or is this specific
functionality that only triggers IRQ 56? (which I note is absent from
mach/irqs.h).

A