MMP2 Interrupt Controller forcing IRQ
Andrei E. Warkentin
andrey.warkentin at gmail.com
Tue Sep 27 00:56:03 EDT 2011
2011/9/27 Mitch Bradley <wmb at firmworks.com>:
> On 9/26/2011 4:40 PM, Andrei E. Warkentin wrote:
>> 2011/9/26 Andrei E. Warkentin<andrey.warkentin at gmail.com>:
>>> 2011/9/26 Mitch Bradley<wmb at firmworks.com>:
>>>> If you write 0x400 to APB_VIRT_BASE + 0x1d008, it will assert interrupt
>>>> 56 .
>>>> You can then clear it by writing 0x400 to APB_VIRT_BASE + 0x1d40c.
>>>> This uses an inter-processor communication unit. Presumably the FIG
>>>> would assert the interrupt and the IRQ 56 handler would clear it.
>>> Awesome! Thanks a lot!!!
>> Hmm. I was hoping that this was really GIC SGI functionality
>> but I guess PJ4 has something completely different. Is there an easy
>> formula for the values written into those two regs and the IRQ value?
>> Or is this specific
>> functionality that only triggers IRQ 56? (which I note is absent from
> It is documented in the Marvell datasheet, which we can't release.
> As far as I know it is specific to this SoC, not a standard ARM thing.
> arch/arm/mach-mmp/include/mach/irqs.h in the Android gingerbread-gold kernel
> #define IRQ_MMP2_IPC2 56
> "IPC" refers to the "InterProcessor Communication" unit.
> There are different bits that you can write to the "set" register to get
> "different" interrupts, but they are all or-ed together at the input to the
> SoC's interrupt controller, so they all appear as INT56. I didn't think it
> was worthwhile to give you all the details of the different IPC unit options
> - nor to I really have time to do so. I hope the recipe I gave you will
> suffice. I presume that the Linux interrupt handling infrastructure will
> take care of the mechanics of registering and dispatching interrupts on this
Oh, absolutely! I was just wondering if there was anything other than 56, but it
definitely works for what I'm doing (in concept, in practice - as soon
as I test it).
Many thanks again for helping me out!
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