[OLPC-devel] Re: NAND flash controller speed.

David Woodhouse dwmw2 at infradead.org
Fri Jun 2 18:52:07 EDT 2006

On Fri, 2006-06-02 at 16:46 -0600, Tom Sylla wrote:
> 3. make timings optimal:
> msr 0x8a00001c 0x110
> msr 0x8a00001b 0x01100110 

It's a small amount faster if you make those 0x010 and 0x00100010 resp.
Any reason you didn't do that? There seems to be enough slack space
between cycles already, without adding more :)


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