[OLPC-devel] Re: NAND flash controller speed.

[Tom Sylla]

David Woodhouse wrote:
> On Fri, 2006-06-02 at 10:25 -0500, Polzin, Steve wrote:
>> I checked with the team and we believe that the 3.5MBytes/sec number is
>> what should be expected for read operations. Sounds like there may be a
>> little room for improvement between 2.7 and 3.5. Can we help getting the
>> main OS code to perform as well as the DOS test application?
> 
> If you could watch my current code with an analyser and see where it's
> slowing down, that would be useful. Tom has done some of that and given
> useful feedback already, but could do with another round.

I am making the other path below (MDMA controller) the higher priority, 
but I spent an hour today looking at this 2.7 vs 3.5 problem. I didn't 
look with an analyzer yet, but I looked through the OLPC configuration, 
and found things that are limiting the performance. Here is my benchmark:

echo -e scale=2\\n16/`(time dd if=/dev/mtd0 of=/dev/null bs=4096 \
count=4096) 2>&1|grep real|cut -c8-12` |bc

This was on a Sparrow platform (internal GX/5536 platform) running at 
the OLPC processor and memory speed. I am using the mtd-2.6 git tree 
from yesterday.

I had 3 configurations:

1. default:
msr 0x8a000015 0xf7c
msr 0x8a000010 0xefe00000 0xffffe007
msr 0x8a00001c 0x111
msr 0x8a00001b 0x01110111

2. add a PCISB region config:
msr 0x88000029 0xefe00001 0xefe01000

3. make timings optimal:
msr 0x8a00001c 0x110
msr 0x8a00001b 0x01100110

DavidW's numbers are from running in config 2. I ran the three configs 
at both 33MHz PCI speed and 66MHz PCI speed.

At 33MHz:
1. 2.62MB/s
2. 2.75MB/s
3. 2.76MB/s
mount "time" of 256MB flash in config 3: 2.70s

At 66MHz:
1. 3.16MB/s
2. 3.26MB/s
3. 3.26MB/s
mount "time" of 256MB flash in config 3: 2.33s

(I don't have the 512MB flash part that is on the OLPC platform, so my 
mount number are probably half of that on OLPC. If someone at OLPC could 
send me the OLPC flash part, it would be great)

Why is the OLPC platform running PCI at 33MHz? We noticed this a while 
back, while we evaluated the OLPC design. I don't believe our evaluation 
has made it to the OLPC team yet (and I didn't realize PCI performance 
made such a difference for flash). Was the PCI speed changed on the 
A-test board? I don't see the reason not to run 66MHz PCI on the OLPC 
platform.

> A limit of 3.5MB/s is very suboptimal though -- it's about an eighth of
> what the chip can do. Another suggestion was made of abusing the IDE
> controller to use MDMA to pull data from the chip... that may well be
> worth exploring.

Yeah, I worked on getting my idea to work yesterday, and initial results 
are pretty encouraging. It is somewhere near 8 or 9 MB/s now (with a DOS 
test only so far). I am still just proving the concept now, once I am 
pretty happy with it, I will write it up and describe the driver work to 
be done to finish it. The board changes for this would be small, just a 
couple of pins hooked up differently on the NAND chip, and no extra 
logic is required on the board. You lose hardware ECC, but you gain some 
of the processor back since it is DMA instead of PIO. The performance 
improvement may make this be the better option.

Tom