[OLPC-devel] RE: NAND flash controller speed.

[David Woodhouse]

On Fri, 2006-06-02 at 10:25 -0500, Polzin, Steve wrote:
> I checked with the team and we believe that the 3.5MBytes/sec number is
> what should be expected for read operations. Sounds like there may be a
> little room for improvement between 2.7 and 3.5. Can we help getting the
> main OS code to perform as well as the DOS test application?

If you could watch my current code with an analyser and see where it's
slowing down, that would be useful. Tom has done some of that and given
useful feedback already, but could do with another round.

A limit of 3.5MB/s is very suboptimal though -- it's about an eighth of
what the chip can do. Another suggestion was made of abusing the IDE
controller to use MDMA to pull data from the chip... that may well be
worth exploring.

The existing OLPC prototype board has pads for an 'IDE flash controller'
chip which connects both to IDE and to the NAND flash. Perhaps one other
option might be to put our own ASIC into that hole. That has cost
implications though -- if we can hook it up directly that would be
cheaper, although we'll have to do ECC in software if we do that.

-- 
dwmw2