[Trac #1374] NAND size is misreported on B3.

[Zarro Boogs per Child]

#1374: NAND size is misreported on B3.
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 Reporter:  cjb       |        Owner:  dwmw2  
     Type:  defect    |       Status:  new    
 Priority:  blocker   |    Milestone:  BTest-3
Component:  hardware  |   Resolution:         
 Keywords:            |  
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Comment (by wmb at firmworks.com):

 The patch I just attached to this ticket

 a) Corrects an error in the previous patch - an | should have been & .

 b) Removes NAND_BBT_PERCHIP from the bad block descriptor options.

 The rationale for (b) is:

 1) There is little value in making the badblock table per-chip when the
 chips are in the same package and soldered down.

 2) Adding per-chip badblock support to the firmware driver would have been
 a lot of trouble for no immediate gain.

 3) Splitting the BBT across chips would have wasted space (two erase
 blocks).

 4) Per-chip BBT would have caused more different code paths to be used for
 different  NAND manufacturers, since some are two-chip per package and
 others are one chip.  While that would be good for the purpose of testing
 the mtd driver, it just adds risk to the OLPC platform.

 We can close this bug when:

 a) New OFW is released with the chip-select fixes (svn 336) (probably
 q2c10)
 b) The kernel patch is committed.
 c) Quanta ECOs the hardware

-- 
Ticket URL: <http://dev.laptop.org/ticket/1374#comment:9>
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