[OLPC-devel] NAND Flash Performance: IDE Interface Hack

[David Woodhouse]

On Fri, 2006-06-16 at 18:53 -0700, Mark J. Foster wrote:
> To relay a message from Steve Polzin at AMD, it looks like the IDE trick 
> won't deliver the performance that we'll need, since software ECC 
> computations are apparently the performance bottleneck (he didn't relay 
> the actual numbers, however).

I think that's based on numbers I sent to Tom yesterday -- reading 16MiB
with the existing driver took 5.9s; reading 16MiB and doing software ECC
on it too 6.6s. It's quite a significant hit.

> It sounds like we'll have to keep digging for other alternative 
> solutions.  Any word on the investigations into using the NAND Flash 
> controller on the Marvell wireless chip? 

That didn't look too promising. The best option looks like a CPLD with
the design that Thomas already has working, perhaps implemented in an
ASIC if that makes it cheaper in bulk. What progress on that?

-- 
dwmw2