scx200_acb: Add a module option to tune the SMB_CLK
Jordan Crouse
jordan.crouse at amd.com
Thu Nov 2 00:19:53 EST 2006
Commit: 56d79bae58f728a1a7211ce295fdbc28b1548547
Parent: 56340040bf66343f6e34ab86bceda2b46470fae7
commit 56d79bae58f728a1a7211ce295fdbc28b1548547
Author: Jordan Crouse <jordan.crouse at amd.com>
AuthorDate: Thu Nov 2 13:23:27 2006 +0800
Commit: David Woodhouse <dwmw2 at infradead.org>
CommitDate: Thu Nov 2 13:23:27 2006 +0800
scx200_acb: Add a module option to tune the SMB_CLK
Add a module option to change the SMB_CLK period. Some platforms
need to be able to tune this value for better performance.
Signed-off-by: David Woodhouse <dwmw2 at infradead.org>
---
drivers/i2c/busses/scx200_acb.c | 15 +++++++++++----
1 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/i2c/busses/scx200_acb.c b/drivers/i2c/busses/scx200_acb.c
index 32aab0d..b4848eb 100644
--- a/drivers/i2c/busses/scx200_acb.c
+++ b/drivers/i2c/busses/scx200_acb.c
@@ -47,6 +47,10 @@ static int base[MAX_DEVICES] = { 0x820,
module_param_array(base, int, NULL, 0);
MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers");
+static unsigned int smbclk = 0x70;
+module_param(smbclk, uint, 0);
+MODULE_PARM_DESC(smbclk, "Specify the SMB_CLK value");
+
#define POLL_TIMEOUT (HZ/5)
enum scx200_acb_state {
@@ -109,6 +113,7 @@ #define ACBCTL1_START 0x01
#define ACBADDR (iface->base + 4)
#define ACBCTL2 (iface->base + 5)
#define ACBCTL2_ENABLE 0x01
+#define ACBCTL3 (iface->base + 6)
/************************************************************************/
@@ -395,11 +400,13 @@ static __init int scx200_acb_probe(struc
{
u8 val;
- /* Disable the ACCESS.bus device and Configure the SCL
- frequency: 16 clock cycles */
- outb(0x70, ACBCTL2);
+ /* Disable the ACCESS.bus device and Configure the SCL */
+
+ outb((smbclk & 0x7F) << 1, ACBCTL2);
+
+ outb((smbclk >> 7) & 0xFF, ACBCTL3);
- if (inb(ACBCTL2) != 0x70) {
+ if (inb(ACBCTL2) != ((smbclk & 0x7F) << 1)) {
pr_debug(NAME ": ACBCTL2 readback failed\n");
return -ENXIO;
}
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