B3 with different RAM chips

[Tiago Marques]

On Tue, Nov 24, 2009 at 2:31 AM, John Watlington <wad at laptop.org> wrote:
>
> Trac it.
>
> No, we have seen nothing that leads us to believe that we have
> memory corruption problems w. B2s.   Software errors are a much
> more likely cause.

Hi John,

Had some more time to debug and it's working fine with OS42's kernel.
The crashed build was running on a 15 day old OLPC Kernel built from
sources but doesn't seem related. As far as I can tell, the crashes
are due to SD card errors when running the OS from the SD card. I
found lots of filesystem errors even when running tests from OS42 when
chrooted to the SD card. I either have a bad SD card(didn't have
problems with it on the XO-1 though, but the cards didn't get tested
there more than two months) or I'm experiencing some corruption for
the external card reader. Seems likely?

Can you provide me with the software or scripts you use to do your
internal SD card testing? I would love to put this card and the other
more reliable SanDisk one I have to find out if it is a problem with
the 1.5 card reader or the SD cards.

Best regards,
Tiago

>
> wad
>
> On Nov 23, 2009, at 6:56 PM, Tiago Marques wrote:
>
>> On Mon, Nov 23, 2009 at 7:19 PM, John Watlington <wad at laptop.org> wrote:
>>>
>>> On Nov 23, 2009, at 1:55 PM, Tiago Marques wrote:
>>>
>>>> On Sun, Nov 22, 2009 at 8:01 PM, Mitch Bradley <wmb at laptop.org> wrote:
>>>>>
>>>>> Tiago Marques wrote:
>>>>>>
>>>>>> Hi,
>>>>>>
>>>>>> The hardware page for the XO 1.5 doesn't show the clockspeed of the
>>>>>> RAM chips used. CAS 3 looks like very aggressive timings for cheap
>>>>>> DDR2 chips.
>>>>>
>>>>> CL3 is in spec for the chips that we were using but not for a new chip
>>>>> that
>>>>> we might start using.
>>>>>
>>>>>> Are you running at 400 or 533?
>>>>>
>>>>> 400
>>>>>>
>>>>>> Doesn't the datasheet specify the appropriate timings?
>>>>>>
>>>>>
>>>>> Of course it does.  The jumper is to tell which timing set to use,
>>>>> depending
>>>>> on which chips are populated.
>>>>
>>>> Ok, I was rather confused when I read:
>>>>
>>>> "I switched the timing to CAS latency 4 (from 3), which ** should meet
>>>> ** specs for this chip."
>>>>
>>>> And was finding rather odd that you didn't had access to specified
>>>> timings.
>>>
>>> We have access to the chip timings, and we have information about how
>>> to program the controller.   But it is still a trial and error process.
>>> Nobody likes to manually verify that the programmable DRAM controller is
>>> actually correctly generating the literally hundreds of timing specs for
>>> a
>>> given chip.  We instead make our best guess at correct values and then
>>> test for proper operation across time and temperature.
>>>
>>> In this case, the chips usually worked with the CAS latency set too low.
>>>
>>> wad
>>>
>>>
>>
>> Ok, I see. Any chance that that procedure might be causing issues
>> related to those errors being generated by overheating problems with
>> B2 hardware? I haven't heard if that has been fixed already. Was it?
>> My 1.5 B2 crashed yesterday in a rather unexplicable fashion and gave
>> me some bad data corruption. Haven't been able to reproduce it though,
>> but it seemed high workload related since I was compiling some
>> packages on an FS in the external SD. Will try to find out more about
>> this.
>>
>> Best regards,
>> Tiago Marques
>>
>
>