B3 with different RAM chips
tiagomnm at gmail.com
Mon Nov 23 18:56:43 EST 2009
On Mon, Nov 23, 2009 at 7:19 PM, John Watlington <wad at laptop.org> wrote:
> On Nov 23, 2009, at 1:55 PM, Tiago Marques wrote:
>> On Sun, Nov 22, 2009 at 8:01 PM, Mitch Bradley <wmb at laptop.org> wrote:
>>> Tiago Marques wrote:
>>>> The hardware page for the XO 1.5 doesn't show the clockspeed of the
>>>> RAM chips used. CAS 3 looks like very aggressive timings for cheap
>>>> DDR2 chips.
>>> CL3 is in spec for the chips that we were using but not for a new chip
>>> we might start using.
>>>> Are you running at 400 or 533?
>>>> Doesn't the datasheet specify the appropriate timings?
>>> Of course it does. The jumper is to tell which timing set to use,
>>> on which chips are populated.
>> Ok, I was rather confused when I read:
>> "I switched the timing to CAS latency 4 (from 3), which ** should meet
>> ** specs for this chip."
>> And was finding rather odd that you didn't had access to specified
> We have access to the chip timings, and we have information about how
> to program the controller. But it is still a trial and error process.
> Nobody likes to manually verify that the programmable DRAM controller is
> actually correctly generating the literally hundreds of timing specs for a
> given chip. We instead make our best guess at correct values and then
> test for proper operation across time and temperature.
> In this case, the chips usually worked with the CAS latency set too low.
Ok, I see. Any chance that that procedure might be causing issues
related to those errors being generated by overheating problems with
B2 hardware? I haven't heard if that has been fixed already. Was it?
My 1.5 B2 crashed yesterday in a rather unexplicable fashion and gave
me some bad data corruption. Haven't been able to reproduce it though,
but it seemed high workload related since I was compiling some
packages on an FS in the external SD. Will try to find out more about
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