[OLPC-devel] NAND Flash Performance: Wireless Chip's Controller

[Mark J. Foster]

Hi, Folks,

The following is Alan Cunningham's (of Marvell) response to our queries 
regarding using the controller on-board the Marvell wireless chip.  
While it is plausible, a variety of concerns, including relatively
modest performance, space issues, potential interference with wireless 
operations, etc, lead us to conclude that this isn't the solution to 
improving NAND Flash performance.

That leaves two primary solutions available to us.  Using the Phison 
NAND controller, as well as the potential CAFE ASIC approach that I'd 
mentioned earlier.  We'll make a decision on which approach to take by 
early next week.

Cheers!
MarkF

-----

1. Can we address this large of Flash memory?

Yes.

2. What is the largest flash memory we can support?

The NAND-Flash Unit was designed to support up to 8Gbits per chip, the
simulation and bench testing was done up to 1Gbits (2 years ago). We can
support up to two chips. We reviewed the datasheet of the Samsung
K9F4G08U0M, and believe we should be interface to this memory.

http://www.samsung.com/Products/Semiconductor/NANDFlash/SLC_LargeBlock/4
Gbit/K9F4G08U0M/K9F4G08U0M.htm



3. What is the fastest read cycle?

Around 176 us to read one page of 2Kbytes without the software overhead.

Throughput = 2048/176 uS =  11.6 Mbps

4. What is the latency through our 88W8388?

The latency would be from the USB interface to the flash interface.
We will have to have SW for error correction, and for descriptor
management.  The path would look something like this:

a. USB transaction to request certain memory range to be read  
b. FW interprets command and programs NAND controller to read data  
c. NAND controller reads data and writes to SQU  
d. NAND controller generates interrupt to FW  
e. FW corrects any errors  
f. FW programs USB to send data to host 

It would take some time to make a good latency estimate.  There is
definitely the initial 176uS for the first page read.  Add to that would
be maybe another 50uS for a wild guess.  That put's it at about 225uS.


5. Would you expect software overhead for Memory transfers from the USB
to the Flash interface?

Yes, this has to be managed by FW.  The two HW blocks cannot talk
directly to each other.

6. What type of testing was done with the Flash two years ago? 


Firmware was not available, all the tests were done using simulation
test vectors, like erase, program, read on both 512 Bytes/page and 2K
Bytes/page, on both Samsung and Toshiba flash memories.
We also did one test by recording the music from the external source
into the NAND flash memories (crossing both memory chips) and then play
it back through the audio interface to the speakers.


7. Other considerations:

a. Power considerations especially in the Mesh
b. Space considerations - Mark brought up this point especially if the
WLAN will be on a module
c. Internal memory utilization and how it would affect Mesh forwarding
tables.

Please let me know if you would like to further pursue using the 88W8388
as the NAND flash interface for OLPC.

Thanks,

Alan