[OLPC-devel] Re: Software action items and status
dwmw2 at infradead.org
Fri Jun 9 11:42:40 EDT 2006
On Fri, 2006-06-09 at 14:51 +0100, David Woodhouse wrote:
> 3). The IDE MDMA hack that Tom has been looking at. The documentation on
> the IDE timing MSR (ATAC_CH0D0_DMA) seems to be explicit that it's
> 66MHz cycles, so by setting tKR and tDR both to zero (i.e. one cycle
> for each of 'active' and 'recovery' time) we ought to be able to
> do 60ns per cycle.
Two errors in the above. Firstly, I just can't count -- 66MHz cycles are
15ns each and not 30ns. Secondly, I was looking at the CS5535 datasheet
not the CS5536, and the CS5536 can't actually go as fast. Its IDE
controller seems to need at least three cycles for each of 'active' and
'recovery' time, so that's a total of 90ns per byte read, or 10.5MiB/s.
Using an ASIC to do 16-bit transfers, with two reads from the NAND chip
for each IDE cycle, we could do 21MiB/s with MDMA. We'd need to arrange
some kind of prefetching for that though. Using UDMA so that we can just
control the timing for ourselves would probably be better.
Again, those are raw buffer read times.
More information about the Devel