[OLPC-devel] Re: NAND flash controller speed.

[David Woodhouse]

On Mon, 2006-06-05 at 15:47 -0600, Ronald G Minnich wrote:
> ow. ow. ow. I don't think it is possible for price and debug reasons to 
> think about an asic from now to this fall.

It's dead simple -- Thomas has a fully working version in a CPLD which
would just need to be adapted to our board. It's basically just a FIFO
and some Reed-Solomon ECC calculation.

> I lost track of this a bit -- why the heck is this so slow? Is this a 
> chipset issue, or what? Are there any usb options we could use, since we 
> have usb on there anyway?

Yes, it's a chipset issue. The NAND flash controller on the CS5536 can't
read bytes from the flash faster than 60ns per cycle, when the chip
could actually manage 25ns cycle times. More importantly, we can't do
PCI burst reads -- we can only do single 32-bit transfers over PCI at a
time. So for each four bytes of data, we get the whole PCI transaction
setup, _then_ it reads four bytes from the NAND chip (slowly), and then
it returns the 32-bit data. It doesn't prefetch the _next_ 4 bytes of
data while we're setting up the next PCI read transction either -- it
sits idle while it's waiting for us to request the next 4 bytes.

Tom had some interesting ideas for connecting the chip up directly to
the IDE bus and abusing MWDMA -- but that approach, cute though it is,
has its own issues and would probably only let us reach half the chip's
speed.

We could _really_ do with raw flash access being about ten times faster
than it is.

-- 
dwmw2