[OLPC-devel] Re: NAND flash controller speed.

[Mark J. Foster]

Hi, David [& AMD]!

Unfortunately, there's no way that the DCON can help with the slow I/O 
that we're seeing from the CS5536 to the Flash chip, since it only 
connects to the GX2's video outputs, has a slow 100 KHz SM-BUS 
connection for register I/O, and connects to a handful of direct I/O 
pins.  It's also the critical path to shipment at the moment, so we 
really can't afford to completely re-architect it.  Sorry about that!

AMD folks, got any tricks up your sleeves?

Best Regards,
MarkF

David Woodhouse wrote:
> We're not really getting decent performance from the NAND flash
> controller on the CS5536. Of the 6 second mount time for my current
> version of JFFS2 on it, about 5 seconds of that is actually reading from
> the chip.
>
> This NAND flash chip ought to be able to read at about 26MiB/s, but
> we're only getting 2.7MiB/s from it. According to Tom, the theoretical
> maximum through the CS5536 is something like 10MiB/s, although even his
> test program under DOS has only ever got 3.5MiB/s.
>
> Is there anything we can do to speed this up -- tenfold? Or should we
> look at connecting the flash differently? All we need is a little ASIC
> which can suck data to/from the chip through a FIFO and do _burst_
> transactions on the PCI bus. Preferably also with ECC calculation.
>
> Can we abuse the DCON chip for this? Are we too late to add such
> functionality, and do we have sane bandwidth to it? Or the EC perhaps?
> Anything else onboard we could think about abusing? All we need is a
> bunch of GPIOs and an 8-bit data bus we can read from at a sensible rate
> (a byte every 25ns, ideally). If we have to do the ECC in software,
> that's probably an acceptable tradeoff for a tenfold increase in raw
> read speed.
>
> Any better ideas?
>
>