#11085 BLOC 1.5-har: XO-1.75 Memory errors

[Zarro Boogs per Child]

#11085: XO-1.75 Memory errors
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           Reporter:  wad                  |       Owner:  wad            
               Type:  defect               |      Status:  assigned       
           Priority:  blocker              |   Milestone:  1.5-hardware-C 
          Component:  ofw - open firmware  |     Version:  1.75-B1        
         Resolution:                       |    Keywords:  XO-1.75, memory
        Next_action:  reproduce            |    Verified:  0              
Deployment_affected:                       |   Blockedby:                 
           Blocking:                       |  
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Changes (by wad):

  * status:  new => assigned


Comment:

 The changes to the memory controller configuration decode to be:

 SDRAM_TIMING_4

  Decrease minimum time in Self-Refresh from 4 to 3

  Increase RD to WR CMD Delay from 2 to 4

  Increase the INIT_COUNT_NOP by 1

 SDRAM_TIMING_5

  Change from 4 active commands per 15 cycles to 4 per 20 cycles

 SDRAM_CTL_1

  Disable Auto-Power-Down

 SDRAM_CTL_4

  Decrease CAS WRITE LATENCY from WL6 to WL5

  Decrease CAS LATENCY from 6 to 4

 SDRAM_CTL_8

  Disable cross-page detection and arbitration, instead using only dynamic
 weight-based arbitration

 PHY_CTL_11
 PHY_CTL_14
 PHY_CTL_10

  These register controlling the DLLs are no longer modified at the start
 of the sequence

 PHY_CTL_3

  Decrease the DQ external delay from 4 to 3

  Decrease the PHY RFIFO RPtr delay value from 4 to 3

 PHY_CTL_7

  DQ PMOS Driver Strength vernier (PHY_DQ_ZPR) increased from 4 to 9

  DQ PMOS Driver Strength (PHY_DQ_ZPDR) decreased from F to 7, disabling
 driver 7

  DQ NMOS Driver Strength vernier (PHY_DQ_ZNR) decreased from 8 to 7

  DQ NMOS Driver Strength (PHY_DQ_ZNDR) decreased from F to 7, disabling
 driver 7

 PHY_CTL_8

  Address/Command PMOS Driver Strength vernier (PHY_ADCM_ZPR) increased
 from 4 to 9

  Address/Command PMOS Driver Strength (PHY_ADCM_ZPDRV) decreased from F to
 7, disabling driver 7

  Address/Command NMOS Driver Strength vernier (PHY_ADCM_ZNR) decreased
 from 8 to 7

  Address/Command NMOS Driver Strength (PHY_ADCM_ZNDRV) decreased from F to
 7, disabling driver 7

 PHY_CTL_9

  Clock NMOS Driver Strength vernier (PHY_CK_ZNR) decreased from 8 to 7

  Clock PMOS Driver Strength vernier (PHY_CK_ZPR) increased from 4 to 7

 PHY_CTL_13

  Increased the DLL reset timer from 2 (512 cycles) to 13 (3328 cycles)

  Changed the PLL phase delay from 68 deg. to 56 deg.

  Disabled DLL Auto Manual Update Enable --- do not issue manual updates to
 the DLL when the MC is idle

  DLL Auto updates remain disabled

 PHY_DLL_CTRL1
 PHY_DLL_CTRL2
 PHY_DLL_CTRL3

  Changed the PLL phase delay from 68 deg. to 56 deg.

  Cleared the tap delay value for testing slave delay chain (unused in
 normal operation)

 PHY_CTRL_14

   The DLL reset has moved to this point in the sequence.

   PHY_DLL_RST is asserted.

   Then PHY_DLL_RST is deasserted, and DLL_UPDATE_EN is asserted.

 PHY_CTRL_WL_SELECT_0
 PHY_CTRL_WL_CTRL_0

    Both these registers (not appearing in the register document) are set
 to 0.

 The memory controller is then initialized in both the new and old cases by
 first asserting the Start Init bit w. CS0 selected in the
 USER_INITIATED_COMMAND0, then by asserting the Start ZQ calibration long
 w. CS0 selected, and then doing 131 dummy reads.

-- 
Ticket URL: <http://dev.laptop.org/ticket/11085#comment:3>
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