#11085 BLOC 1.5-har: XO-1.75 Memory errors

[Zarro Boogs per Child]

#11085: XO-1.75 Memory errors
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           Reporter:  wad                  |       Owner:  wad            
               Type:  defect               |      Status:  assigned       
           Priority:  blocker              |   Milestone:  1.5-hardware-C 
          Component:  ofw - open firmware  |     Version:  1.75-B1        
         Resolution:                       |    Keywords:  XO-1.75, memory
        Next_action:  reproduce            |    Verified:  0              
Deployment_affected:                       |   Blockedby:                 
           Blocking:                       |  
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Comment(by wad):

 Changes suggested by Marvell from memory config in Q4B05d:

 SDRAM_CONFIG0_TYPE1 (new: 00046430)

  Don't set Dynamic ODT bits

  Increase ODT RTT_Nom from 1 to 2

  Increase output driver strength from 0 to 1

 SDRAM_TIMING1 (new: 91D500CA)

  Increased Internal Write-to-READ delay from 4 to 7

 SDRAM_TIMING2 (new: 777703B4)

  Increased tRP from 6 to 7

  Increased tRRD from 4 to 7

  Increased tRDC from 6 to 7

  Increased tWR from 6 to 7

  Increased Refresh to Active interval (tRFC) from 0x2C to 0x3B

 SDRAM_TIMING3 (new: C202406F)

  Exit self-refresh to first DLL locked command delay increased from 0 to 2

  Exit self-refresh to first non-DLL locked command delay increased from 48
 to 64

  Exit precharge power-down w. DLL frozen to first DLL locked command delay
 increased from 10 to 14 (data sheet says to use 7 for DDR3).

  Exit power-down w. DLL on to valid command delay increased from 3 to 7.

 SDRAM_TIMING4 (new: 46830209)

  Increase tCKE from 3 to 4

  Increased INIT_COUNT from 0x4F to 0x68

  Decreased RD to WR command delay from 2 to 1

  Increased RESET_COUNT from 40 to 64

  Increased INIT_COUNT_NOP from 0x187 to 0x209

 SDRAM_TIMING5 (new: 00140101)

  Increased the ACTIVE-to-PRECHARGE command (tRAS) from 15 to 20

  Decreased tFAW from 20 to 16 cycles.

 SDRAM_CTRL2 (new: 0f000000)

  Cleared SDRAM Line boundary (currently set to line_32b)

 SDRAM_CTRL4 (new: 00c08009)

  Cleared Fast Bank addressing

 SDRAM_CTRL6_SDRAM_ODT_CTRL (new: 00000201)

  Now assert ODT1 when writing to CS1

 SDRAM_CTRL7_SDRAM_ODT_CTRL2 (new: 0100000a)

  Termination is now controlled by both ODT0 and ODT1

 SDRAM_CTRL8_SDRAM_ODT_CTRL2 (new: 00000133)

  Enable cross-page detection and arbitration

 SDRAM_CTRL11_ARB_WEIGHTS_FAST_QUEUE (new: 03030303)

  Increase the arbitration weight for all masters from 1 to 3

 PHY_CTRL13 (new: 201000f8)

  Decrease the DLL reset timer from 3328 cycles back to 512

  Change PLL phase delay from 56 deg. to 85 deg.

  Enable auto manual update of DLL

  Set bit in testing slave delay chain (even though not enabled)

 PHY_DLL_CTRL1, CTRL2, CTRL3 (new: 001070f0)

  Changed DLL phase delay select from 56 deg. to 85 deg.

  Set reserved bits 14:12

  Set bit in testing slave delay chain

 At this point, the recommended configuration diverges from the existing
 one.  The recommended one first initializes the DRAM controller, then
 asserts DLL update enable.  It finally asserts a reserved bit in the user
 initiated command register.

 The existing sequence first asserts a DLL reset, then a DLL update enable,
 then finally initializes the memory controller.

-- 
Ticket URL: <http://dev.laptop.org/ticket/11085#comment:7>
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