#9694 NORM 1.5-fir: Memory speed slower in OFW than Phoenix

[Zarro Boogs per Child]

#9694: Memory speed slower in OFW than Phoenix
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           Reporter:  wmb at firmworks.com    |       Owner:  wmb at firmworks.com   
               Type:  defect               |      Status:  assigned            
           Priority:  normal               |   Milestone:  1.5-firmware        
          Component:  ofw - open firmware  |     Version:  Development firmware
         Resolution:                       |    Keywords:                      
        Next_action:  reproduce            |    Verified:  0                   
Deployment_affected:                       |   Blockedby:                      
           Blocking:                       |  
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Changes (by wmb at firmworks.com):

  * status:  new => assigned


Comment:

 One difference between OFW's and Phoenix's memory controller settings is
 the "interleave type" field that controls which CPU address bits go to the
 BA[2:0] (bank address) bits on the memory chips.  That could affect memory
 speed on some workloads by changing the level of concurrency.

 In order to adopt the Phoenix settings, it is necessary to know the
 mapping from CPU address bits to memory chip multiplexed address pins for
 different interleave types.  The reason that is needed is because it
 affects the value you must write to the memory chips during the "MRS" and
 "EMRS" mode setting steps.

 That mapping is not documented in the Vx855 Programmer's Manual.  The
 mapping for the interleave type that OFW currently uses can be inferred
 from the coreboot source code which uses that same setting (which is why
 OFW uses that setting), but I don't have any similar way to infer the
 mapping for Phoenix's interleave type.  I have a question out to Via,
 asking them to provide the mapping information.

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Ticket URL: <http://dev.laptop.org/ticket/9694#comment:3>
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