#9646 BLOC 1.5-F11: Switch to 24bpp

[Zarro Boogs per Child]

#9646: Switch to 24bpp
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           Reporter:  cjb                  |       Owner:  wmb at firmworks.com
               Type:  defect               |      Status:  new              
           Priority:  blocker              |   Milestone:  1.5-F11          
          Component:  ofw - open firmware  |     Version:  not specified    
         Resolution:                       |    Keywords:                   
        Next_action:  code                 |    Verified:  0                
Deployment_affected:                       |   Blockedby:                   
           Blocking:                       |  
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Comment(by wmb at firmworks.com):

 Good work.  The shift formulation has a typo - the second 27 should be 22
 - which is what is killing the green.  Furthermore it is rather sensitive
 to the compiler promoting to the types to int instead of u_int, so the
 right shifts become arithmetic - which is why the red is bleeding into the
 other colors.  The shift formulation is good in assembly language, because
 shift instructions often encode as shorter instructions than ANDs, due to
 the fact that the shift count can be expressed in fewer bits than full
 bitmasks.

 In this case, dsd's AND formulation is just fine, and probably less likely
 to break in the future.  The speed difference between the two is probably
 unmeasurable in the context of this application.

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Ticket URL: <http://dev.laptop.org/ticket/9646#comment:11>
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