#5703 HIGH 8.2.0 (: Lid switch detection is unreliable.

[Zarro Boogs per Child]

#5703: Lid switch detection is unreliable.
-------------------------+--------------------------------------------------
   Reporter:  cjb        |       Owner:  dilinger            
       Type:  defect     |      Status:  new                 
   Priority:  high       |   Milestone:  8.2.0 (was Update.2)
  Component:  kernel     |     Version:                      
 Resolution:             |    Keywords:  power               
Next_action:  never set  |    Verified:  0                   
  Blockedby:             |    Blocking:  6590                
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Comment(by dsaxena):

 Replying to [comment:12 wmb at firmworks.com]:
 > I used OFW to characterize the behavior of the various registers related
 to lid detection.  Notable results:
 >
 >
 > a) Edge events show up in the edge status registers regardless of the
 setting of the edge enable bits.
 >
 >
 > b) The master GPIO event enable bit in register +0xb8 disables/enables
 the forwarding of edge events to the PM_GPE0_STS register as expected.
 >
 >
 > c) The individual positive and negative edge enable bits control the
 forwarding of edge events to PM_GPE0_STS - but gated by (b) - almost as
 expected; the exception being case 0.
 >
 >
 >   0) Pos disabled, Neg disabled:  pos edges cause events; neg edges do
 not
 >
 >   1) Pos disabled, Neg enabled:  neg edges cause events; pos edges do
 not
 >
 >   2) Pos enabled, Neg disabled:  pos edges cause events; neg edges do
 not
 >
 >   3) Pos enabled, Neg enabled:  both edges cause events
 >
 >
 >
 > d) Transitioning either edge enable from enabled to disabled causes an
 event if the master enable (b) is on.  In this case neither edge status
 bit is set.
 >
 >
 > e) If either edge enable is on, the readback register (+0xb0) does not
 accurately report the current state of the lid switch.
 >
 >
 > f) After you turn off both edge enables, it takes between 62 and 90 usec
 before the lid switch state reads back correctly.  I expect this timing is
 controlled by the 32 kHz sampling clock - between 2 and 3 cycles of that
 clock depending on the phase.  So it seems that 100 uS would be a safe
 delay time between turning off the enables and reading the state.  (Not
 that I would recommend such a delay in an interrupt handler.)

 +1 on no delay in the interrupt handler. The new code only uses modes 1
 (pos disabled, neg enabled) and 2 (both enabled) and I think we can safely
 rely on those to detect the cases we care about instead of trying to
 readback the register. We also always disable the master enable bit before
 we switch event states, so we won't receive spurious events due to (d).

-- 
Ticket URL: <http://dev.laptop.org/ticket/5703#comment:15>
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