[Trac #1193] Disable CPU access to EC RAM and I/O

[Zarro Boogs per Child]

#1193: Disable CPU access to EC RAM and I/O
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 Reporter:  wmb at firmworks.com    |       Owner:  ray.tseng at quantatw.com
     Type:  defect               |      Status:  new                   
 Priority:  high                 |   Milestone:  BTest-3               
Component:  embedded controller  |    Keywords:                        
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 It is currently possible for the main CPU to access arbitrary EC RAM and
 I/O resources via the 381,382,383 I/O port dance.  For security reasons,
 we need to disable that and provide EC commands to access specific
 information that we currently get via that path.

 Here are some things that we current access via ports 381..383.  Please
 add to this list as necessary:

 a) Polling for game key presses in fast-boot firmware (if a game key is
 pressed, the interactive boot path is used)

 b) Controlling write-protect for the SPI FLASH

 c) Turning the keyboard controller functionality on and off for the
 purpose of programming SPI FLASH (there may be a new command for this
 already)

 d) Programming the SPI FLASH.

 e) Controlling the keyboard LEDs (which are going away, so this is
 probably moot)

 f) Resetting the wireless LAN module

 g) Accessing battery state information

 h) Bit-banging the 1-wire battery status line for recovering bricked
 batteries


 We may want to leave direct access available to the firmware at early
 system firmware startup, and then turn it off when we latch on the SPI
 FLASH write protect.  That would let the system firmware perform SPI
 reflashing using the current direct access method.

-- 
Ticket URL: <http://dev.laptop.org/ticket/1193>
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