[Trac #947] DCONLOAD goes high at S3 entry and exit

[Zarro Boogs per Child]

#947: DCONLOAD goes high at S3 entry and exit
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 Reporter:  wmb at firmworks.com  |        Owner:  wad    
     Type:  defect             |       Status:  new    
 Priority:  blocker            |    Milestone:  BTest-3
Component:  hardware           |   Resolution:         
 Keywords:                     |  
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Changes (by wmb at firmworks.com):

 * cc: smithbone at gmail.com (added)

Comment:

 I have confirmed the tri-state hypothesis and the effectiveness of a pull-
 down in preventing DCONLOAD glitches.

 a) First test: connected 2K2 resistor from DCONLOAD to ground, thus
 forming a voltage divider with the existing pull-up resistor.  In this
 configuration, with DCONLOAD set to low via the GPIO, the signal glitched
 to 0.6V at S3 entry and exit.  0.6V is the expected value for 10K up / 2K2
 down voltage divider driven from 3.3V.  So the tri-state hypothesis is
 confirmed.

 b) Second test: removed the 10K pullup (R188), leaving the 2K2 pulldown
 connected.  In this configuration, with DCONLOAD set to low via the GPIO,
 the signal remained low throughout the S3 cycle.

 In configuration (b), the LCD screen retains the correct display image
 while suspended (with the unmodified board, entry to S3 caused the display
 to fade out).

 However, there is still a remaining problem: when waking up from S3
 (initiated by briefly pressing the power button), the LCD screen usually
 immediately goes blank (actually almost blank - it has closely-spaced dim
 vertical lines).   I saw one time where this didn't happen - the screen
 stayed intact upon wakeup - but most of the time the screen blanks.  This
 is not caused by DCONLOAD glitches; I have verified that DCONLOAD remains
 solidly low while this is happening.

-- 
Ticket URL: <http://dev.laptop.org/ticket/947#comment:3>
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