[Trac #835] Investigate 4M PTE/TLB caching on the Geode

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#835: Investigate 4M PTE/TLB caching on the Geode
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 Reporter:  marcelo  |        Owner:  marcelo
     Type:  defect   |       Status:  new    
 Priority:  normal   |    Milestone:  BTest-3
Component:  kernel   |   Resolution:         
 Keywords:           |  
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Comment (by JordanCrouse):

 Tom's comments (for posterity):

 {{{
 Geode 4M paging support is fully compatible with x86 architecture 4M
 caching. It is advertised properly in CPUID. It *should* be enabled
 and in use in the OLPC builds automatically. (someone with an olpc
 handy could dump the tables and check easily)

 The bit pointed out in "Data Memory Configuration Register" (address
 1800) is for disabling the PTE cache for debug. The 4M PTE cache is
 enabled since the bit is clear:

 http://dev.laptop.org/attachment/ticket/109/OLPC.prs

 The "L2 TLB/DTE Index Register" you pointed out is also for debug, it
 is a way to dump out the various paging caches. The bits set in that
 register don't affect operation.

 So I guess the summation is that no "special" support is required, the
 registers should be set properly, and all that is needed to verify is
 that the kernel doesn't do something silly and not use them.
 }}}

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Ticket URL: <http://dev.laptop.org/ticket/835#comment:2>
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