[Trac #281] Geode vsync/hsync polarity strangeness

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#281: Geode vsync/hsync polarity strangeness
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 Reporter:  dwmw2     |        Owner:  JordanCrouse
     Type:  defect    |       Status:  new         
 Priority:  normal    |    Milestone:  BTest-1     
Component:  hardware  |   Resolution:              
 Keywords:            |  
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Comment (by JordanCrouse):

 It turns out that in flat panel mode, we should only be changing the sync
 polarity in the DF_PT2 register (bits 29 and 30), and leaving the CRT
 polarity to the default in DF_DCFG register (i.e., both set to 0).  Its an
 interesting side effect that the inverse is true (leaving the DF_PT2 bits
 at default and changing the DF_DCFG bits also has the correct behavior),
 but it is more correct to be changing CRT bits while in CRT mode and FP
 bits while in FP mode.   While in CRT mode, only modify the DF_DCFG
 register accordingly - it is a very bad thing to try to access the flat
 planel registers in CRT mode.

 [[br]]
 So to summarize - to set active high sync for the DCON / flatpanel:[[br]]

 DF_DCFG &= ~0x300 (clear bits 8 and 9)[[br]]
 DF_PT2 |= 0x00C00000 (set bits 22 and 23)[[br]]
 [[br]]
 To set active low sync:[[br]]

 DF_DCFG &= ~0x300 (clear bits 8 and 9)[[br]]
 DF_PT2 &= ~0x00C00000 (clear bits 22 and 23)[[br]]

 Once my sick network comes back - I'll push the code changes to the
 olpc-2.6 tree.  I also need to examine X to see if it is doing the right
 thing or not.  Still remains open, and assigned to me.

-- 
Ticket URL: <http://dev.laptop.org/ticket/281#comment:2>
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